Arrangement with p-doped and n-doped semiconductor layers and method for producing the same

ABSTRACT

An arrangement having p-doped semiconductor layers and n-doped semiconductor layers which exhibits transitions between the p-doped semiconductor layers and n-doped semiconductor layers, the transitions displaying a Zener breakdown upon application of a voltage characteristic of a transition, a plurality of transitions between p-doped semiconductor layers and n-doped semiconductor layers being present, and the characteristic voltages additively make up the breakdown voltage of the entire arrangement. Also described is a method for manufacturing the arrangement.

FIELD OF THE INVENTION

The present invention relates to an arrangement having p-doped andn-doped semiconductor layers which exhibits transitions between thep-doped semiconductor layers and n-doped semiconductor layers, thetransitions displaying a Zener breakdown upon application of a voltagecharacteristic of a transition. The present invention further concerns amethod for manufacturing the arrangement according to the presentinvention.

BACKGROUND OF THE INVENTION

The use of semiconductor components to limit voltages is known. Zenerdiodes (Z diodes), in particular, are used for this purpose. If Zenerdiodes are operated in the blocking or reverse direction, they display apronounced breakdown behavior at comparatively low breakdown voltages.The value of the breakdown voltage of a diode depends substantially onthe doping concentration of the semiconductor material. In highly dopeddiodes, a very narrow barrier layer forms, so that high electrical fieldstrengths above the p-n transition are present upon application of evensmall reverse voltages.

If the field strength exceeds a value of approximately 10⁶ V/cm, valenceelectrons in the vicinity of the almost charge-carrier-free p-ntransition can be pulled out of their bonds. In the band model, thiseffect is represented as tunneling through the forbidden band. At lowvoltages below the breakdown voltage (also called the Zener voltage),only the (usually negligibly low) reverse current flows. When the Zenervoltage is reached, the current rises sharply due to charge carrieremission, thus preventing any further increase in voltage. At breakdownvoltages below 4.5 V, the result is a “pure Zener” breakdown. At higherbreakdown voltages there is another competing breakdown effect, namelythe so-called avalanche breakdown. This predominates at voltages above 7V, and results substantially from avalanching impact ionizations in thesemiconductor. Because of its defined and reversible breakdown, a Zenerdiode is suitable as a voltage limiter. If two Zener diodes areconnected together in anti-serial fashion, i.e. in series but withopposite polarity, symmetrical breakdown behavior will be obtained.

A circuit of this kind is illustrated in FIG. 6, which depicts a firstZener diode 110 and a second Zener diode 112 connected anti-serially.Arrangements of this kind are used for voltage limiting in order tolimit both polarities of a voltage applied to contacts 114, 116.

FIG. 7 shows the corresponding current/voltage characteristic of thecircuit depicted in FIG. 6. In the diagram of FIG. 7, the currentflowing through Zener diodes 110, 112 is plotted against the voltageapplied to contacts 114, 116. Ignoring path resistances and the rise inbreakdown voltage resulting from self-heating, the breakdown voltage ofthe arrangement is UZ1+UF, where UZ1 denotes the breakdown voltage ofone of the Zener diodes (which in the present case are assumed to beidentical) and UF is the voltage drop of a diode in the forwarddirection. If a voltage limiting circuit of this kind is to be designedfor higher limit voltages, however, the positive breakdown voltagetemperature response, as seen in FIG. 7, occurs. In FIG. 7, a solid lineshows a characteristic at room temperature (RT) and a dashed line showsa characteristic at much higher temperature (HT). The positivetemperature response seen here results principally from the fact that indiodes designed for higher breakdown voltages, avalanche breakdown ispredominant.

The temperature dependence of the characteristic shown in FIG. 7 isundesirable. The voltage limiting circuit of FIG. 6 additionally has thedisadvantage that two separate components are needed to implement it,entailing additional circuit complexity.

SUMMARY OF THE INVENTION

In an example embodiment of the present invention a plurality oftransitions between p-doped semiconductor layers and n-dopedsemiconductor layers are present; and characteristic voltages additivelymake up a breakdown voltage of the entire arrangement. Through thepresent invention it is no longer necessary to use two separatecomponents to bring about voltage limitation for both polarities of thevoltage. Instead, a single arrangement having multiple transitionsbetween p-doped semiconductor layers and n-doped semiconductor layersprovides voltage limitation for both polarities. Since thecharacteristic voltages of the transitions at which the transitionsexhibit a Zener breakdown moreover additively make up the breakdownvoltage of the entire arrangement, it is possible to select a low levelfor the individual breakdown voltages and nevertheless, because of theaddition of the individual breakdown voltages, effect limitation to acomparatively high voltage. Since the Zener effect greatly predominatesat the small characteristic voltages of the individual transitions(which for example can be 4.2 V), (i.e. avalanche breakdown still playsno role or only a subordinate role), a practicallytemperature-independent characteristic curve may be made availabledespite the high limit voltage that is provided.

The semiconductor layers may be highly doped. A high level of dopingresults in a low breakdown voltage and thus, in the desired temperature,independence of the apparatus.

The semiconductor layers may exhibit constant doping allowing simplemanufacture. With constant doping the breakdown voltage is moreovercalculable because of the identical properties of the transitionsbetween layers.

Another embodiment provides p-doped semiconductor layers and n-dopedsemiconductor layers which are doped at the same concentration. Thisresults in a uniform configuration of the depletion zone in both then-doped semiconductor layers and the p-doped semiconductor layers. Thisallows the layer sequence to be configured uniformly.

Another embodiment provides for the p-doped semiconductor layers to format least two groups that are doped at different concentrations. Thismakes it possible to obtain a characteristic that is asymmetrical withrespect to voltage polarity, unlike the case of uniform doping of all p−semiconductor layers and all − semiconductor layers, which yields asymmetrical characteristic. Voltage limitations that differ depending onthe polarity of the voltage can thus be made available.

For the same reason, another embodiment provides n-doped semiconductorlayers to form at least two groups that are doped at differentconcentrations.

Another embodiment provides for the semiconductor layers to be arrangedon an n-doped substrate.

Another embodiment provides for the semiconductor layers to be arrangedon a p-doped substrate. In this embodiment there is no dependence on aspecific doping of the substrate, thereby making the arrangementflexible in terms of manufacture and utilization.

The doping type of the semiconductor layer farthest away from thesubstrate may correspond to the doping type of the substrate.

The doping type of the semiconductor layer farthest away from thesubstrate may be different from the doping type of the substrateproviding flexibility in terms of the manufacture and field ofapplication of the arrangement, and no limitation to a specific dopingtype for the outermost semiconductor layers.

The semiconductor layers may have a thickness of approximately 4 μm.Such a thickness is suitable, i.e. sufficiently thick, in the context ofthe feasible breakthrough voltages of the individual transitions and thedepletion zone thicknesses related thereto. The thickness prevents theminority charge carriers injected through the transitions polarized inthe forward direction from reaching a space charge zone of an adjacenttransition that is reverse-polarized. The entire arrangement would“fire” (thyristor effect) if not designed in this way.

The substrate may have a thickness of approximately 500 μm. A substratethickness on this order ensures, inter alia, sufficient mechanicalstability.

The doping concentration may be provided in the region of 2×10¹⁹atoms/cm³. At such a high doping concentration, a Zener effect isobtained in each transition at the desired low Zener voltage, and thuswith a correspondingly low temperature dependence.

In a specific embodiment, approximately ten transitions between p-dopedsemiconductor layers and n-doped semiconductor layers are provided. AtZener voltages in the region of 4.2 V and conducting voltages in theregion of 0.7, an overall breakdown voltage of, for example, 50 V isobtained, without significant temperature dependence. If this level ofvoltage limitation were to be implemented with a conventional design,i.e. with individual Zener diodes, the overwhelming dominance of theavalanche effect would result in a considerable and in some casesintolerable temperature dependence.

The arrangement may have on its upper side and lower side respectivemetal contacts which extend over their entire surface. The arrangementis thereby prepared for the further processing that is usually performedon semiconductor components.

The semiconductor layers may be silicon layers. The high doping levelsand the desired layer structure may be brought about using silicon.

The present invention further relates to a method for manufacturing anarrangement having p-doped and n-doped semiconductor layers whichexhibits transitions between the p-doped semiconductor layers andn-doped semiconductor layers, the transitions displaying a Zenerbreakdown upon application of a voltage characteristic of a transition,a plurality of transitions between p-doped semiconductor layers andn-doped semiconductor layers being present, and the characteristicvoltages additively making up the breakdown voltage of the entirearrangement, the method comprising application of the semiconductorlayers by epitaxy. Epitaxy provides a suitable method for building uplayer arrangements that constitute the present invention.

The epitaxy may take place at approximately 1180° C. This temperatureallows defect-free layer formation.

The epitaxy may be performed at a growth rate of approximately 4 μm/min.This rate ensures a high-quality layer structure with a sufficientlyrapid manufacturing method.

Metal contacts may be sputtered onto the upper side and lower side ofthe arrangement. By way of these metal contacts, which may cover theentire upper side and the entire lower side of the arrangement, thearrangement is prepared for further processing. The sputtering methodhas proven particularly reliable for the application of thin metallayers.

The arrangement may be divided into individual chips after the metalcontacts are sputtered on. For example, a silicon substrate that isinitially used may have a diameter of 125 mm. The chips resulting fromthe method, which are produced, for example, with the use of a circularsaw, may then have a surface area of, for example, 20 mm².

The edges of the chips may be removed. If the chips are produced, forexample, by a sawing operation, crystal disruptions that have a negativeeffect on the electrical properties of the component are created at thechip edge. This disrupted semiconductor region at the chip edge is thenremoved, for example to a depth of 50 μm. This can be achieved, forexample, by etching in KOH. Etching is often performed after the chiphas been soldered at its front and rear sides into a copper housing.Further packaging is then performed in a manner common in diodetechnology.

In addition to construction of the layer arrangement by epitaxy, thinsilicon disks may be assembled by wafer bonding. Variability thus existsin terms of manufacture.

With a corresponding layer arrangement made up of p-doped and n-dopedsemiconductor layers, bipolar voltage limitation are available withnegligible temperature dependence. The breakdown voltage of individualp-n transitions may be selected, through appropriate doping, so thatpractically only Zener breakdown occurs. Because the layer arrangementis configured in such a way that the breakdown voltages of theindividual p-n transitions additively make up the breakdown voltage ofthe overall arrangement, voltage limitation may be achieved even forhigh voltages with a low temperature dependence.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a cross sectional view of an arrangement according to thepresent invention.

FIG. 2 is a characteristic curve of an arrangement as shown in FIG. 1.

FIG. 3 is a doping profile of an arrangement as shown in FIG. 1.

FIG. 4 is a cross sectional view of a further embodiment of anarrangement according to the present invention.

FIG. 5 is a characteristic curve of an arrangement as shown in FIG. 4.

FIG. 6 is a schematic layout of a circuit according to the existing art.

FIG. 7 is a characteristic curve of the arrangement as shown in FIG. 6.

DETAILED DESCRIPTION

FIG. 1 schematically shows a cross section of an arrangement accordingto the present invention. A plurality of p-doped semiconductor layers 12and n-doped semiconductor layers 14 are arranged on an n-doped siliconsubstrate 10. A plurality of semiconductor transitions are presentbetween p-doped semiconductor layers 12 and n-doped semiconductor layers14. P-doped semiconductor layers 12 have a thickness TP, while n-dopedsemiconductor layers have a thickness TN. In the present case,thicknesses TP and TN are approximately identical and are approximately4 μm. The substrate has a thickness TS of approx. 525 μm in the presentexample. Since a total of ten p-doped semiconductor layers and tenn-doped semiconductor layers 14 are arranged on substrate 10, the totalthickness T of the arrangement resulting from these data is 605 μm. Inthe present example, silicon is selected as the semiconductor. Locatedon n-doped substrate 10 and the uppermost semiconductor layer, which inthe present case is an n-doped semiconductor layer 14, are metalcontacts 16, 18 that were applied with a sputtering procedure.Semiconductor layers 12, 14 each have a constant doping level of approx.2×10¹⁹ atoms/cm³. Layers 12, 14 were applied by epitaxy onto therespective layer beneath. In an example embodiment, the epitaxy takesplace in such a way that a temperature of 1180° C. and a growth rate of4 μm/min is selected. In the present example as shown in FIG. 1, thelayer arrangement is selected that the uppermost layer and bottommostlayer (substrate) have the same doping type, in the present casen-doping. The two outer semiconductor layers may also exhibit p-doping.The outer layers may have different doping types, in the context of bothan n-type substrate and a p-type substrate.

FIG. 2 shows in simplified fashion a characteristic curve of thearrangement shown in FIG. 1. If a voltage U that is positive as comparedto electrode 16 is applied to metal electrode 18, no current (other thana reverse current) flows until reverse voltage UZ is reached. If anattempt is made to increase voltage U even further, the current throughthe arrangement rises sharply as a result of the Zener breakdowns at theindividual transitions between the semiconductor layers. Since thearrangement is symmetrically constructed, reversing the polarity of theapplied voltage U results in the same electrical behavior with theopposite sign. Assuming n p-doped epitaxial layers and n-doped epitaxiallayers, the equation for the breakdown voltage UZ is:UZ=n*(UZ1+UF)where UZ1 is the breakdown voltage of an individual transition, and UFis the forward voltage of an individual p-n diode. The solid line inFIG. 2 shows the current/voltage behavior of the arrangement at roomtemperature (RT). The dashed line shows the behavior at highertemperatures (HT). Until very high currents are reached, temperature haspractically no influence on the curve. Only at very high currentdensities, approximately in the region above 200 A/cm², is anon-negligible positive temperature coefficient once again present.

FIG. 3 depicts the doping profile of the arrangement shown in FIG. 1,the number density of doping atoms N being plotted against location x.The solid lines denote n-doped silicon, and the dashed lines denotep-doped silicon. The left side of the diagram in FIG. 3 corresponds tothe n-doped silicon layer of FIG. 1 that is adjacent to metal electrode18, while the right side of the diagram in FIG. 3 corresponds tosubstrate 10 in FIG. 1 that is adjacent to metal electrode 16 of FIG. 1.A constant doping concentration of 2×10¹⁹ atoms/cm³ is present.

FIG. 4 schematically shows a cross section of a further embodiment of anarrangement according to the present invention that results in voltagelimitation regardless of the voltage polarity. As previously stated, thearrangement shown in FIG. 1 has a characteristic curve that issymmetrical in terms of the polarity of the applied voltage. Thearrangement depicted in FIG. 4, however, yields an asymmetricalcharacteristic curve. The particular feature of this arrangement is thattwo types of p-doped semiconductor layers are present. A first p-dopedsemiconductor layer 20 has a lower doping concentration than a secondp+-doped semiconductor layer 22. The doping concentration of the n-typesemiconductor layers is uniform. This yields diodes having differentbreakdown voltages, corresponding to the n−(p+p) and (p+p)−ntransitions. When the diodes are loaded in the reverse direction, thebreakdown voltage UZ1 of the (p+p)n diode is greater than the breakdownvoltage UZ2 of the n(p+p) diode. Assuming n transitions, a voltage atmetal contact 18 that is positive with respect to metal contact 16results in a breakdown voltageUZ=n*(UZ2+UF).

If the polarity of the voltage is reversed, the resulting breakdownvoltage isUZ=−n*(UZ1+UF).

The arrangement shown in FIG. 4 is variable in principle in terms of theoutermost semiconductor layers and in terms of doping types. Forexample, a p-type substrate can also be used instead of an n-typesubstrate. In the case of a p-type substrate, more highly doped n+-typelayers and less highly doped n-type layers would correspondingly beused. The outermost layers of the semiconductor arrangement can in turnbe identical or different in terms of doping type.

FIG. 5 shows a characteristic curve of an arrangement as shown in FIG.4. With suitable dimensioning in terms of both geometry andconcentrations, the result is practically temperature-independentcharacteristic curves as depicted in FIG. 5. FIG. 5 corresponds in ageneral configuration to FIG. 2, while using the asymmetrical curve.

The description above of the exemplary embodiments of the presentinvention is provided for illustrative purposes only, and not forpurposes of limiting the invention. A variety of changes andmodifications are possible in the context of the present inventionwithout departing from the scope of the invention or its equivalents.

1. An arrangement, comprising: p-doped semiconductor layers; n-dopedsemiconductor layers; and a plurality of transitions arranged betweenthe p-doped semiconductor layers and the n-doped semiconductor layers,the transitions displaying a Zener breakdown upon application of acharacteristic voltage for each of the transitions, wherein: thecharacteristic voltages of the transitions additively correspond to abreakdown voltage of the arrangement, the p-doped semiconductor layersand the n-doped semiconductor layers are highly doped, the p-dopedsemiconductor layers form at least two groups doped at differentconcentrations, a highly doped layer of the p-doped semiconductor layersbeing doped at about 2×10¹⁸ atoms/cm³, the n-doped semiconductor layersform at least two groups that are doped at different concentrations, ahighly doped layer of the n-doped semiconductor layers being doped atabout 2×10¹⁸ atoms/cm³, the p-doped semiconductor layers and the n-dopedsemiconductor layers exhibit a constant doping, and the p-dopedsemiconductor layers and the n-doped semiconductor layers are doped at asame concentration, wherein the p-doped semiconductor layers and then-doped semiconductor layers have a thickness of approximately 4 μm. 2.The arrangement according to claim 1, further comprising: an n-dopedsubstrate on which are arranged the p-doped semiconductor layers and then-doped semiconductor layers.
 3. The arrangement according to claim 2,wherein a doping type of a semiconductor layer farthest away from then-doped substrate corresponds to a doping type of the n-doped substrate.4. The arrangement according to claim 2, wherein a doping type of asemiconductor layer farthest away from the n-doped substrate isdifferent than a doping type of the n-doped substrate.
 5. Thearrangement according to claim 2, wherein the n-doped substrate has athickness of approximately 500 μm.
 6. The arrangement according to claim1, further comprising: a p-doped substrate on which are arranged thep-doped semiconductor layers and the n-doped semiconductor layers. 7.The arrangement according to claim 6, wherein a doping type of asemiconductor layer farthest away from the p-doped substrate correspondsto a doping type of the p-doped substrate.
 8. The arrangement accordingto claim 6, wherein a doping type of a semiconductor layer farthest awayfrom the p-doped substrate is different than a doping type of thep-doped substrate.
 9. The arrangement according to claim 7, wherein thep-doped substrate has a thickness of approximately 500 μm.
 10. Thearrangement according to claim 1, wherein a concentration of doping forthe p-doped semiconductor layers and the n-doped semiconductor layers isapproximately 2×10¹⁹ atoms/cm³.
 11. The arrangement according to claim1, wherein ten transitions are provided between the p-dopedsemiconductor layers and the n-doped semiconductor layers.
 12. Thearrangement according to claim 1, further comprising: metal contactsarranged over an entire respective surface of an upper side and a lowerside of the arrangement.
 13. The arrangement according to claim 1,wherein the n-doped semiconductor layers and the p-doped semiconductorlayers are silicon layers.